Cache Behaviour of the SPEC 95

نویسندگان

  • Sanjoy Dasgupta
  • Edouard Servan-Schreiber
چکیده

Previous cache studies are becoming rather outdated, since they deal with older benchmarks (such as those in SPEC92) and smaller cache conngurations than are now feasible. We remedy this situation by performing a battery of cache tests on several interesting programs in the SPEC95 suite. The applications of chief interest to us are those that are represent current trends in computing, such as ijpeg, perl and database programs. We try out a variety of key cache conngurations and do some analyses of second-level caches. The results generally corroborate older studies, with some subtle and interesting diierences. Some conclusions are: (1) a block size of 32 bytes remains optimal for rst-level caches; (2) LRU buys little more than random replacement; (3) going beyond 2-associativity results in little improvement; (4) the 2:1 \cache rule-of-thumb" is highly application-dependent; (5) second-level caches do not need to be very large, and there is little point in pushing their associativity beyond 2-way or making their replacement policy LRU; and (6) second-level caches may warrant blocks of 64 bytes or more, depending upon their size. We also found some idiosyncrasies of diierent classes of programs; for instance, the optimal block size for our database application vortex was lower than that for our other benchmarks, indicating highly non-sequential accesses.

برای دانلود رایگان متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Memory Behavior of the SPEC2000 Benchmark Suite

The SPEC CPU benchmarks are frequently used in computer architecture research. The newly released SPEC’2000 benchmarks consist of fourteen floating point and twelve integer applications. In this paper we present measurements of number of cache misses for all the applications for a variety of cache configurations. Prior studies have shown that SPEC benchmarks do not put much stress on the memory...

متن کامل

Cache Sharing Sensitivity of SPEC CPU2006 Benchmarks

This report presents results of the experiments assessing the sensitivity of SPEC CPU2006 benchmarks to several types of cache and memory bus sharing induced by artificial workloads on an Intel Core 2 based Xeon processor.

متن کامل

Improving TLB performance

In modern computers, TLB can be in the critical path of a memory access. Good TLB performance is essential to good overall performance of a machine 5]. The objective of our project is to improve the TLB performance. In our project, we propose two approaches to improve TLB performance. One approach is to use TLB prefetching, and the other is to have an additional level TLB (so we have a multi-le...

متن کامل

An Architectural Assessment of SPEC CPU Benchmark Relevance

SPEC compute intensive benchmarks are often used to evaluate processors in high-performance systems. However, such evaluations are valid only if these benchmarks are representative of more comprehensive real workloads. I present a comparative architectural analysis of SPEC CPU benchmarks and the more realistic SPEC Java Server benchmark. This analysis indicates the integer subset of CPU benchma...

متن کامل

Generation, Validation and Analysis of SPEC CPU2006 Simulation Points Based on Branch, Memory and TLB Characteristics

The SPEC CPU2006 suite, released in Aug 2006 is the current industry-standard, CPUintensive benchmark suite, created from a collection of popular modern workloads. But, these workloads take machine weeks to months of time when fed to cycle accurate simulators and have widely varying behavior even over large scales of time [1]. It is to be noted that we do not see simulation based papers using S...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 1996